I am a Postdoctoral Researcher at New York University (August 2024–present), advised by Prof. Ramesh Karri. My current research lies at the intersection of large language models and electronic design automation (LLM4EDA), with a focus on RTL generation, formal verification, hardware security, and design-space exploration.

Before joining NYU, I received my Ph.D. in Electronic Science and Technology from Shanghai Jiao Tong University (September 2019–June 2024) under the supervision of Prof. Weikang Qian. During my Ph.D., my research focused on approximate computing for energy-efficient hardware and logic and transistor-level synthesis, including approximate multiplier optimization, approximate logic decomposition, symbolic probability propagation, and exact transistor-network synthesis. I was also a visiting scholar at the University of Alberta (January–December 2023) with Prof. Jie Han.

Education & Appointments

• Postdoctoral Researcher, New York University — August 2024–present
• Ph.D. in Electronic Science and Technology, Shanghai Jiao Tong University — September 2019–June 2024
• Visiting Scholar, University of Alberta — January–December 2023
• B.Eng. in Communication Engineering, Xidian University — October 2015–June 2019

Research Interests

• Large language models for electronic design automation
• RTL generation, verification, and hardware security
• Logic and transistor-level synthesis
• Approximate computing for energy-efficient AI hardware

Selected Highlights

• CoEvoP&R: co-evolving placement objectives with routing feedback via large language models (ASP-DAC 2027).
• TrojanLoC: an LLM-based framework for RTL Trojan detection, classification, and line-level localization (ICCAD 2026).
• VeriThoughts: reasoning models and formal verification for automated Verilog generation (NeurIPS 2025).
• Hybrid-NL2SVA: RAG and fine-tuning for natural-language-to-SystemVerilog assertion generation (MLCAD 2025).
• GUIDE: an open, modular platform for GenAI-driven digital design education (DATE 2026).
• MiniTNtk: SAT-based exact synthesis for minimizing transistor networks (ICCAD 2023).

Please see my publications, research overview, service and honors, or download my CV for more information.

News

• 2026: CoEvoP&R was accepted at ASP-DAC 2027.
• 2026: CoEvoP&R was selected for the Google Cloud Research Credits Program ($5,000).
• 2026: TrojanLoC was accepted as a regular paper at ICCAD 2026.
• 2026: GUIDE and LLM4PQC appeared at DATE 2026.
• 2025: VeriThoughts was accepted at NeurIPS 2025.
• 2025: Hybrid-NL2SVA appeared at MLCAD 2025.